Low power devices are often designed such that they exploit periods of inactivity to deactivate non-necessary functions and enter an “idle” mode. For instance, it is common to deactivate the high speed crystal oscillator (operating at 10s of MHz) that provides the timing reference for the digital and also possibly analogue components. This reduces the power consumption of the device dramatically.
In many cases, it is necessary to be able to maintain an accurate timing reference during this idle period. For instance, a communications protocol implemented by the device may require that the device is reactivated to either send or receive messages at a particular point in time. Alternatively, if the device is woken up by an external signal, it may be necessary to determine accurately how much time has elapsed since the device entered low power mode.
An example of such a device is a Bluetooth communications circuit. The Bluetooth standard requires the maintenance of a transmission slot timer (control clock) operating at a rate of 1.6 kHz, which is allowed a maximum frequency drift of 250 ppm while in low power mode and a maximum timing jitter of 10 μs on awakening. This timer is used to determine when the device should awaken to receive or transmit data.
Typically, when the Bluetooth device is embedded in a larger system such as a mobile phone, there will be an external timing reference available during the low power mode. Such a reference is typically derived from a 32.768 kHz crystal oscillator, which consumes little power and is extremely cheap. Alternatively, an internal low-frequency oscillator may be used.
One approach is to make use of the low-power reference signal directly to determine when to leave low power mode. However, this requires that, e.g., software calculate the number of low power reference clock cycles that corresponds to the required number of control clock cycles prior to entering low power mode, and then calculate a further fractional correction on leaving low power mode. This requires processing time, which limits the amount of time that can be spent in the low power mode.
An alternative approach is to use a fractional divider circuit to derive the 1.6 kHz control clock from the available low-power reference signal. A fractional divider circuit produces an output signal with frequency FC with the following relationship to the reference clock frequency FLP:
      F    LP    =            (              M        +                  N                      P            DIV                              )        ×          F      C      
PDIV is the period of the fractional divider, M is the integer part of the division ratio, and N is the magnitude of the fractional part (N<PDIV). The ratio is generally determined once for a given input and output frequency, and so does not represent a continuous overhead.
A standard implementation of a fractional divider is based on a simple integer divider (which generates a single output pulse once every M input pulses), with the integer division ratio alternated between M and (M+1) such that, over PDIV output clocks, the average division ratio is correct. An example of a digital circuit to perform this operation is shown in prior art FIG. 1. In FIG. 1 there is disclosed a fractional divider means 102 operable to produce an output signal with a frequency FC with the following relation to a reference clock frequency FLP:
      F    LP    =            (              M        +                  N                      P            DIV                              )        *          F      C      
The fractional divider means 102 comprises an accumulator means 108 operable to keep track of the total timing error. The fractional divider means 102 also comprises an integer divider means 112 connected to the accumulator means 108 and to a reference clock A operable to divide the reference clock A with an integer division ratio of either M or M+1. The fractional divider means 102 also comprises a ratio selector means 114 connected to the integer divider means 112 operable to keep the total timing error minimised symmetrically around zero. The fractional divider means 102 also comprises an adding means 120 connected to the accumulator means 108, a subtracting means 122 connected to the accumulator means 108, and a multiplexer means 124 connected to the adding means 120, the subtracting means 122 and the ratio selector means 114. As is apparent from FIG. 1, the adding means 120 and the subtracting means 122 are also connected to the ratio selector means 114. The output clock from the fractional divider means 102 is denoted B.
Every time a division ratio of M is selected, the output clock is produced with a period that is N/PDIV input clock cycles shorter than the ideal output clock period. Alternatively, when a division ratio of M+1 is selected the output clock is produced with a period that is (1−N/PDIV) input clock cycles longer than the ideal output clock period. The accumulator 108 is used to keep track of the total timing error: every time a division ratio of M is used, the accumulator is incremented by N, while every time a division ratio of M+1 is used, the accumulator is decremented by (PDIV−N). At the beginning of each output clock cycle, the circuit 114 determines which division ratio (M or M+1) will cause the least timing error with respect to the ideal clock output, and uses that division ratio.
An example of how this is performed is shown in prior art FIG. 2. In this example, the fractional part is set to 0.1 (i.e., N=1, PDIV=10). To generate the first cycle of the output clock, a division ratio of M is chosen. This results in an error of 0.1 (i.e., the output clock is produced 0.1 periods of the input clock too early). Had the ratio M+1 been used, the resulting output clock would instead have come 0.9 input clock cycles too late. At the beginning of each new output clock cycle, the same decision is made with the error gradually accumulating. By output cycle 4, the error has reached 0.5 (corresponding to an accumulator value 5): at this stage, choosing a division ratio of M would produce an error of +0.6, while choosing a ratio of M+1 would produce a smaller absolute error of −0.4. Hence, the circuit chooses a division ratio M+1.
The problem with this method of clock division is that, at any given instant, the error (jitter) from the output clock to the ideal clock can be up to half of an input clock cycle. For the case of a 32.768 kHz clock this would result in a jitter of 15 μs, which violates the 10 μs jitter requirements for the Bluetooth control clock.